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Config.h 3deab29845fbfa978ce8b488505b05f6be8cf4e4 (3deab298) Text, 2.56 KB
Tff7b72#Tff7b72include T8b949e"ROM.h"
Tff7b72#Tff7b72ifndef CONFIG_H
Tff7b72#Tff7b72define CONFIG_H
Tff7b72#Tff7b72define MAJ_VERS 0x01
Tff7b72#Tff7b72define MIN_VERS 0x03
Tff7b72#Tff7b72define MCU_328P 0x90
Tff7b72#Tff7b72define MCU_1284P 0x91
Tff7b72#Tff7b72define MODE_HOST 0x11
Tff7b72#Tff7b72define MODE_TNC 0x12
Tff7b72#Tff7b72if defined(__AVR_ATmega328P__)
Tff7b72#Tff7b72define MCU_VARIANT MCU_328P
Tff7b72#Tff7b72warning "Firmware is being compiled for atmega328p based boards"
Tff7b72#Tff7b72elif defined(__AVR_ATmega1284P__)
Tff7b72#Tff7b72define MCU_VARIANT MCU_1284P
Tff7b72#Tff7b72warning "Firmware is being compiled for atmega1284p based boards"
Tff7b72#Tff7b72else
Tff7b72#Tff7b72error "The firmware cannot be compiled for the selected MCU variant"
Tff7b72#Tff7b72endif
Tff7b72#Tff7b72define MTU 500
Tff7b72#Tff7b72define SINGLE_MTU 255
Tff7b72#Tff7b72define HEADER_L 1
Tff7b72#Tff7b72define CMD_L 4
T8b949e// MCU dependent configuration parameters
Tff7b72#Tff7b72if MCU_VARIANT == MCU_328P
Tff7b72const Tffa657int Te6edf3pin_cs Tff7b72= T79c0ff7Tb4b4b4;
Tff7b72const Tffa657int Te6edf3pin_reset Tff7b72= T79c0ff6Tb4b4b4;
Tff7b72const Tffa657int Te6edf3pin_dio Tff7b72= T79c0ff2Tb4b4b4;
Tff7b72const Tffa657int Te6edf3pin_led_rx Tff7b72= T79c0ff5Tb4b4b4;
Tff7b72const Tffa657int Te6edf3pin_led_tx Tff7b72= T79c0ff4Tb4b4b4;
Tff7b72#Tff7b72define FLOW_CONTROL_ENABLED true
Tff7b72#Tff7b72define QUEUE_SIZE 0
Tff7b72#Tff7b72define EEPROM_SIZE 512
Tff7b72#Tff7b72define EEPROM_OFFSET EEPROM_SIZE-EEPROM_RESERVED
Tff7b72#Tff7b72endif
Tff7b72#Tff7b72if MCU_VARIANT == MCU_1284P
Tff7b72const Tffa657int Te6edf3pin_cs Tff7b72= T79c0ff4Tb4b4b4;
Tff7b72const Tffa657int Te6edf3pin_reset Tff7b72= T79c0ff3Tb4b4b4;
Tff7b72const Tffa657int Te6edf3pin_dio Tff7b72= T79c0ff2Tb4b4b4;
Tff7b72const Tffa657int Te6edf3pin_led_rx Tff7b72= T79c0ff12Tb4b4b4;
Tff7b72const Tffa657int Te6edf3pin_led_tx Tff7b72= T79c0ff13Tb4b4b4;
Tff7b72#Tff7b72define FLOW_CONTROL_ENABLED true
Tff7b72#Tff7b72define QUEUE_SIZE 24
Tff7b72#Tff7b72define EEPROM_SIZE 4096
Tff7b72#Tff7b72define EEPROM_OFFSET EEPROM_SIZE-EEPROM_RESERVED
Tff7b72#Tff7b72endif
Tff7b72#Tff7b72define eeprom_addr(a) (a+EEPROM_OFFSET)
T8b949e// MCU independent configuration parameters
Tff7b72const Tffa657long Te6edf3serial_baudrate Tff7b72= T79c0ff115200Tb4b4b4;
Tff7b72const Tffa657int Te6edf3rssi_offset Tff7b72= T79c0ff164Tb4b4b4;
Tff7b72const Tffa657int Te6edf3lora_rx_turnaround_ms Tff7b72= T79c0ff50Tb4b4b4;
T8b949e// Default LoRa settings
Tffa657int Te6edf3lora_sf Tff7b72= T79c0ff0Tb4b4b4;
Tffa657int Te6edf3lora_cr Tff7b72= T79c0ff5Tb4b4b4;
Tffa657int Te6edf3lora_txp Tff7b72= T79c0ff0xFFTb4b4b4;
Tffa657uint32_t Te6edf3lora_bw Tff7b72= T79c0ff0Tb4b4b4;
Tffa657uint32_t Te6edf3lora_freq Tff7b72= T79c0ff0Tb4b4b4;
T8b949e// Operational variables
Tffa657bool Te6edf3radio_locked Tff7b72= Tffa657trueTb4b4b4;
Tffa657bool Te6edf3radio_online Tff7b72= Tffa657falseTb4b4b4;
Tffa657bool Te6edf3hw_ready Tff7b72= Tffa657falseTb4b4b4;
Tffa657uint8_t Te6edf3op_mode Tff7b72= Te6edf3MODE_HOSTTb4b4b4;
Tffa657uint8_t Te6edf3model Tff7b72= T79c0ff0x00Tb4b4b4;
Tffa657uint8_t Te6edf3hwrev Tff7b72= T79c0ff0x00Tb4b4b4;
Tffa657int Te6edf3last_rssi Tff7b72= T79c0ff-164Tb4b4b4;
Tffa657size_t Te6edf3read_len Tff7b72= T79c0ff0Tb4b4b4;
Tffa657uint8_t Te6edf3seq Tff7b72= T79c0ff0xFFTb4b4b4;
Tffa657uint8_t Te6edf3pbufTb4b4b4[Te6edf3MTUTb4b4b4]Tb4b4b4;
Tffa657uint8_t Te6edf3sbufTb4b4b4[Te6edf3MTUTb4b4b4]Tb4b4b4;
Tffa657uint8_t Te6edf3cbufTb4b4b4[Te6edf3CMD_LTb4b4b4]Tb4b4b4;
Tffa657uint32_t Te6edf3stat_rx Tff7b72= T79c0ff0Tb4b4b4;
Tffa657uint32_t Te6edf3stat_tx Tff7b72= T79c0ff0Tb4b4b4;
Tffa657bool Te6edf3outbound_ready Tff7b72= Tffa657falseTb4b4b4;
Tffa657bool Te6edf3stat_signal_detected Tff7b72= Tffa657falseTb4b4b4;
Tffa657bool Te6edf3stat_signal_synced Tff7b72= Tffa657falseTb4b4b4;
Tffa657bool Te6edf3stat_rx_ongoing Tff7b72= Tffa657falseTb4b4b4;
Tffa657bool Te6edf3dcd Tff7b72= Tffa657falseTb4b4b4;
Tffa657bool Te6edf3dcd_led Tff7b72= Tffa657falseTb4b4b4;
Tffa657bool Te6edf3dcd_waiting Tff7b72= Tffa657falseTb4b4b4;
Tffa657uint16_t Te6edf3dcd_count Tff7b72= T79c0ff0Tb4b4b4;
Tffa657uint16_t Te6edf3dcd_threshold Tff7b72= T79c0ff15Tb4b4b4;
Tffa657uint32_t Te6edf3status_interval_ms Tff7b72= T79c0ff3Tb4b4b4;
Tffa657uint32_t Te6edf3last_status_update Tff7b72= T79c0ff0Tb4b4b4;
T8b949e// Status flags
Tff7b72const Tffa657uint8_t Te6edf3SIG_DETECT Tff7b72= T79c0ff0x01Tb4b4b4;
Tff7b72const Tffa657uint8_t Te6edf3SIG_SYNCED Tff7b72= T79c0ff0x02Tb4b4b4;
Tff7b72const Tffa657uint8_t Te6edf3RX_ONGOING Tff7b72= T79c0ff0x04Tb4b4b4;
Tff7b72#Tff7b72endif
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